RoCEv2: Add DCQCN congestion control#1430
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# Conflicts: # axi/axi-stream/rtl/AxiStreamCompact.vhd
Correct indentation of generic/type/generic-map closing parens, move the XBAR_CONFIG_C assignment operator, and rename local process variables to camelCase (variable_004) with their colon alignment.
The rewritten AxiStreamCompact preserves payload data, so a full-keep beat passes straight through. Update the expected output beat to the correct tData (0x44332211) instead of the old zeroed value.
- AxiStreamCompact: replace local countKeepBytes() with onesCount() from StdRtlPkg - AxiStreamMon: add optional frameUpdate output (registered onto statusClk when COMMON_CLK_G); delete duplicate ethernet/RoCEv2/rtl/AxiStreamMonDcqcn.vhd and switch TokenBucket caller to surf.AxiStreamMon - RoceEngineWrapper: change mAxisMetaDataSlave default from AXI_STREAM_SLAVE_INIT_C to AXI_STREAM_SLAVE_FORCE_C - RocePkg: rename SURF_DATA_STREAM_CONFIG_C to ROCEV2_AXIS_CONFIG_C - Rename RoCEv2 RTL modules with RoCEv2 prefix: AlphaUpdate, AxisBucket, Dcqcn, RateDecProc, RateIncProc, TokenBucket, TokenCalc
- IpV4Engine, IpV4EngineTx, UdpEngineWrapper: rename DSCP_G -> ROCEV2_DSCP_G and ECN_G -> ROCEV2_ECN_G to mark the IPv4 traffic-class fields as RoCEv2-driven; no caller bindings to update - python/surf/ethernet/roce: split _RoceEngine.py into _RoceEngine.py (RoceEngine) and _Dcqcn.py (Dcqcn), one PyRogue device per file - Replace placeholder descriptions on Dcqcn.CnpCounter and Dcqcn.CnpCounterReset with descriptions of the rollover counter and its soft-reset behavior
DSCP and ECN are general IPv4 ToS/Traffic Class fields per RFC 2474 and RFC 3168, not specific to RoCEv2. The ROCEV2_ prefix mislabeled general-purpose IpV4Engine generics; revert the names.
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I tested this using slaclab/Simple-10GbE-RUDP-KCU105-Example#11 + rogue@pre-release (latest) and confirmed that it works |
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Summary
Adds DCQCN (Data Center Quantized Congestion Notification) congestion control to the RoCEv2 engine, plus the supporting IPv4/UDP and AXI-Stream changes needed to carry ECN/CNP signaling.
Originally developed on
FilMarini/surf:dcqcnEn; migrated here and merged up to currentpre-release(conflict-free).Changes
DCQCN core (new modules under
ethernet/RoCEv2/rtl/)Dcqcn.vhd,AlphaUpdate.vhd,RateIncProc.vhd,RateDecProc.vhd— rate control state machineTokenBucket.vhd,AxisBucket.vhd,TokenCalc.vhd— token-bucket rate limiterAxiStreamMonDcqcn.vhd— rate/throughput monitoringRoceEngineWrapper.vhd— wiring +Dcqcn_enenable parameter; CNP output portECN/CNP signaling path
IpV4Engine.vhd/IpV4EngineTx.vhd— DSCP + ECN fields in the IPv4 headerEthMacRxRoCEv2.vhd,RocePkg.vhd,UdpEngineWrapper.vhd— plumbingSgmii88E1111LvdsUltraScale.vhd—RoceV2_enparameter for the RJ45 PHY pathblue-rdma regen —
mkQP.v,mkAxisTransportLayer.v,mkTransportLayer.v(QP destroy fix, RNR-retry-with-fragmentation fix, full 2-byte address, sequential pipeline for timing)AXI-Stream —
AxiStreamCompact.vhdreworked for the congestion-control data pathSoftware —
python/surf/ethernet/roce/_RoceEngine.pyDCQCN RemoteVariable register mapReview notes
AxiStreamCompact.vhdis a full rewrite of an existing shared surf module (not a new file). This is the main item to scrutinize — confirm it preserves behavior for existing non-DCQCN users.Dcqcn_engeneric; default-off behavior should be confirmed.Status
Draft — pending FW review and register cross-check.